http://www.embeddedinsights.com/channels/2011/02/01/dark-silicon-redux-system-design-problem-or-fundamental-law/ Shedding Light on the Hidden World of Embedded Systems Mon, 28 Jul 2014 16:18:37 -0400 hourly 1 http://wordpress.org/?v=3.0 http://www.embeddedinsights.com/channels/2011/02/01/dark-silicon-redux-system-design-problem-or-fundamental-law/#comment-5292 Leigh Wed, 02 Feb 2011 17:58:25 +0000 http://www.embeddedinsights.com/channels/?p=433#comment-5292 One existing approach to the 'dark silicon' problem is kind of like the UCSD/MIT approach. Employ hundreds of simpler, lighter weight cores that are far more energy-efficient than typical SMP/Von Neumann/shared/virtual memory cores such as x86 CPUs. Then arrange them on silicon in a MIMD, hierarchical mesh of interconnect so they can still express highly complex programs such as H.264 video compression. Decompose application architectures so that the cores only do single tasks. Each core would have efficient, dedicated, distributed memories, instead of constantly churning virtual/shared memory, (do allow shared SDRAM access for larger data chunks such as video frame buffers). Oh, and to ease programmability and software design/debug have the MIMD interconnect enforce task/core 'encapsulation' in the object-oriented sense, enabled in silicon circuits... this encapsulation being crucial to practical programmability and debug of complex software systems on hundreds or thousands of cores. For an example of this architecture, see Nethra's 'Ambric-Architecture' chips with over 300 cores per chip. As an example, these massively-parallel-processor-array (MPPA) chips are deployed in a 13,000 core X-ray processing system of 40 TeraOPS and 2,000 GMACS compute, in under 500 W. This 40-chip system is housed in an ATCA chassis. If the same chassis could possibly be stuffed with 40 Intel CPUs or Nvidia GPU's of equivalent compute, it would melt into a smoking puddle of aluminum/burnt plastic from over 6KW of energy (GPUs). See www.nethra.us.com/products_am2045_overview.php for a description of the current generation chip. The next gen of this type of architecture can push toward 1K cores and enormous compute on one die without a 'dark silicon' problem. The key to practical use is programmability which has been solved by the programming model, the encapsulation enforced by the self-synchronizing interconnect, and mature design/debug tools. One existing approach to the ‘dark silicon’ problem is kind of like the UCSD/MIT approach. Employ hundreds of simpler, lighter weight cores that are far more energy-efficient than typical SMP/Von Neumann/shared/virtual memory cores such as x86 CPUs. Then arrange them on silicon in a MIMD, hierarchical mesh of interconnect so they can still express highly complex programs such as H.264 video compression. Decompose application architectures so that the cores only do single tasks. Each core would have efficient, dedicated, distributed memories, instead of constantly churning virtual/shared memory, (do allow shared SDRAM access for larger data chunks such as video frame buffers). Oh, and to ease programmability and software design/debug have the MIMD interconnect enforce task/core ‘encapsulation’ in the object-oriented sense, enabled in silicon circuits… this encapsulation being crucial to practical programmability and debug of complex software systems on hundreds or thousands of cores. For an example of this architecture, see Nethra’s ‘Ambric-Architecture’ chips with over 300 cores per chip. As an example, these massively-parallel-processor-array (MPPA) chips are deployed in a 13,000 core X-ray processing system of 40 TeraOPS and 2,000 GMACS compute, in under 500 W. This 40-chip system is housed in an ATCA chassis. If the same chassis could possibly be stuffed with 40 Intel CPUs or Nvidia GPU’s of equivalent compute, it would melt into a smoking puddle of aluminum/burnt plastic from over 6KW of energy (GPUs). See http://www.nethra.us.com/products_am2045_overview.php for a description of the current generation chip. The next gen of this type of architecture can push toward 1K cores and enormous compute on one die without a ‘dark silicon’ problem. The key to practical use is programmability which has been solved by the programming model, the encapsulation enforced by the self-synchronizing interconnect, and mature design/debug tools.

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