[Editor's Note: This was originally posted on the Embedded Master] 

In the previous post in this series I pointed out that the “sweet spot” clock rate for active power consumption for some microcontrollers is lower than the maximum operating clock rate for that part. However, looking only at the rated power consumption of these microcontrollers at a steady always-on operating state ignores the fact that many low-power microcontrollers employ on-chip resources that can significantly impact the overall energy consumption of the part as the system transitions through multiple operating scenarios.

For low power applications, designers usually focus on the overall operating system energy draw rather than the peak draw. This focus on overall power efficiency justifies the additional design, build, and testing complexity of using low power and sleep modes when the system does not need to draw on the full processing capacity of the processor. In fact, many low power constrained systems spend the majority of their operating time in some type of sleep mode and transition to full active mode only when needed. This relationship begins to hint at why using only a single uA/MHz benchmark is insufficient to evaluate a processor’s energy performance.

There is a variety of low power modes available to processor architectures. Shutting down just the CPU and leaving all of the other on-chip resources functional is one type of sleep mode. Deeper sleep modes can turn off individual or all peripherals until the only on-chip resource drawing current is for RAM retention. Always-on resources may include a power supervisor circuit with brown-out and power-on-reset functions; these functions must be enabled 100% of the time because the events they are designed to detect cannot be predicted.

So in addition to active power draw, low power designers need to understand the system’s static or leakage current draw when the system is inactive. Another important metric is wake-up-time – the amount of time it takes the system to transition from a low-power mode to the active operating mode because the system clock needs to stabilize. The longer it takes the system clock to stabilize, the more energy is wasted because the system is performing no useful work during that time.

A DMA controller is an on-chip resource that affects a system’s power consumption by offloading the task of moving data from one location to another, say from a peripheral to memory, from the expensive CPU to the much cheaper to operate DMA controller. The following chart from an Atmel whitepaper demonstrates the value of using a DMA controller to offload the CPU, especially as the data rate increases. However, effectively using the DMA can add a level of complexity for the developer because using the DMA controller is not an automated process.

Some microcontrollers, such as from Atmel and Energy Micro, allow developers to configure the DMA controller and peripherals, through some type of peripheral controller, so that they can collect or transmit data autonomously without waking the CPU. On some devices, the autonomous data transfer can even include direct data transfers from one peripheral to another. The following chart from Energy Micro’s technology description demonstrates the type of energy reduction autonomous peripherals can create. The caveat is that the developer needs to create the highly autonomous setup as there are no tools that can perform this task automatically at this time.

On-chip accelerators not only speed up the execution of frequent computations or data transformations, they also do it for less energy than performing those functions with a software engine. Other types of on-chip resources that save energy draw can include ROM-based firmware, such as being adopted by NXP and Texas Instruments on some of their parts. There are countless approaches available to chip architects to minimize energy consumption, but they each involve trade-offs in system speed, current consumption, and accuracy that are appropriate differently to each type of application. This makes it difficult to develop a single benchmark for comparing energy consumption between processors that overlap capabilities but target slightly different application spaces.

[Editor's Note: This was originally posted in the Embedded Master] 

In the previous post in this series I asked whether reporting uA/MHz is an appropriate way to characterize the energy profile of a processor. In this post, I assume uA/Mhz is appropriate for you and offer some suggestions of additional information you might want processor vendors to include with this benchmark when they use it. I will explore how uA/MHz is insufficient for many comparisons in the follow-on post in this series.

One problem with reporting a processor’s power draw as uA/MHz is that this value is not constant across the entire operating range of the processor. Consider the chart for the Texas Instruments MSP430F5438A operating at 3V, from 256-kbyte Flash, and with an integrated LDO. This processor has an operating range up to 25MHz, and the value of uA/MIPS ranges from 230 to 356 uA/MIPS across the full operating range. Additionally, the energy sweet spot for this device is at 8MHz. Using the part at higher (and lower) clock rates consumes more energy per additional unit of processing performance.

Adrian Valenzuela, TI MSP430 MCU Product Marketing Engineer at Texas Instruments shares that many designers using this part operate it at its energy sweet spot of 8MHz precisely because it is most energy efficient at that clock rate rather than at its highest operating speed.

The chart for Microchip’s PIC16LF1823 device illustrates another way to visualize the energy sweet spot for a processor. In this example, the energy sweet spot is at the “knee” in the curve, which is at approximately 16 MHz – again short of the device’s maximum operating clock rate of 32 MHz. 

At a minimum, if a processor vendor is going to specify a uA/MHz (or MIPS) metric, they should also specify the operating frequency of the device to realize that energy efficiency sweet spot. To provide a sense of the processor’s energy efficiency across the full operating range, the processor vendor could include the uA/MHz metric at the device’s highest operating frequency – the implied assumption is that the energy efficiency varies with clock rate in some proportion between these two operating points.

Using a single-value uA/MHz as an energy metric is further complicated when you consider usage profiles that include waking-up from standby or low power modes. In the next post in this series I will explore the challenges of comparing energy efficiency between different processors when the benchmarking parameters differ, such as what kind of software is executing, what is the compiler and memory efficiency, and what peripherals are active?

[Editor's Note: This was originally posted on the Embedded Master] 

In the previous Extreme Processing post about low cost processing options, I touched on what techniques processor vendors are using to drive down the price of their value line devices. However, the focus of these companies is not just on low price, but on delivering the best parts to match the performance, power, and price demands across the entire processing spectrum. Semir Haddad, Marketing Manager of the 32-bit ARM microcontrollers at STMicroelectronics, shares “Our goal ultimately is to have one [processor part] for each use case in the embedded world, from the lowest-cost to the highest-end.”

In addition to extreme low cost parts, there is increasing demand for processors that support longer battery life. Similar to low cost processor announcements, there is a bit of marketing specmanship when releasing a device that drives down the leading edge of the lowest energy usage by a microcontroller. The ARM Cortex-M3 based EFM32 Gecko microcontrollers from EnergyMicro claims a 180 μA/MHz active mode power consumption. Texas Instruments’ 16-bit ultra-low power line of MSP430 microcontrollers claims a 165 μA/MIPs active mode power consumption. Microchip’s new 8-bit PIC1xF182x microcontrollers claim a less than 50 μA/MHz active current consumption.

There are many ways to explore and compare low power measurements, and there have been a number of exchanges between the companies including white papers and YouTube videos. We can explore some of these claims over the next few posts and discussions, but for this post, I would like to focus on whether the use of μA/MHz benchmark is appropriate or if there is a better way for low power processor vendors to communicate their power consumption to you. In the case of the Texas Instruments part, 1 MHz = 1 MIPS when there is no CPU clock divider.

If the μA/MHz benchmark for active operation is appropriate for you, is there any additional information you need disclosed with the benchmark so that you can make an educated judgment and comparison between similar and competing parts? The goal here is to help suppliers communicate the information you to more quickly make decisions. I have a list of characteristics I think you might need along with the benchmark value, and I will share it with you in the next post after you have a chance to discuss it here.

If the μA/MHz benchmark is not appropriate for you, what would be a better way to communicate a device’s relevant power consumption scenarios? I suspect the μA/MHz benchmark is popular in the same way that MIPS benchmarks are popular – because they are a single, simple number that is easy to measure and compare. The goal here is to highlight how to get the information you most need more quickly, easily, and consistently. I have some charts and tables to share with you in the follow-on post.