Targets: Audio, Communication & Wired, General Purpose, Imaging & Video, Mobile & Wireless

Coreworks FireWorks Block Diagram

The FireWorks is a 5-stage pipeline modified 32-bit Harvard RISC architecture featuring a high-speed programming interface and specific DSP instructions. This processor can be configured to include (or not) a hardware multiplier, a barrel shifter, and a serial divider. It supports external interrupt requests. The FireWorks also supports configurable caches for instructions and data.

The FireWorks IP (intellectual property) core uses approximately 0.05 mm2 in a 65nm technology, consuming less than 7.5 mW at the maximum frequency. When working as a standalone processor, the FireWorks can be classified as a general purpose embedded processor. However, Coreworks provides SideWorks, a hardware accelerator, which interacts with the FireWorks through the system bus. When integrated with SideWorks, the target applications include, but are not limited to, multimedia and communications. In general, any computing intensive DSP application can be performed with FireWorks+SideWorks.

Coreworks provides an FPGA development platform for evaluation of FireWorks. The FireWorks evaluation platform consists of a PC connected to an FPGA board. On the PC the user is able to write, assemble, and upload programs to FireWorks. The company provides a routine which allows for FireWorks to print information on the host PC screen. The communication between PC and FPGA is implemented using the Coreworks proprietary Core Access Networks technology.