Digital Core Design

Digital Core Design


Targets: General Purpose

Digital Core Design DP8051CPU Block Diagram

The DP8051CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced PMU (power management unit).

The DP8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051CPU. The Harvard configuration separates the internal data and program buses; the von Neumann configuration uses common program and external data bus. The DP8051CPU has a Pipelined RISC architecture and executes 120 to 300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.45 to 14.73 times faster than the original 80C51 at the same frequency.

The DP8051CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

Each of the DCD's 8051 Core has built in support for DCD Hardware Debug System called DoCD. It is a real-time hardware debugger which provides debugging capability of a whole SoC (System on Chip). The DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user-defined peripherals.