Targets: Imaging & Video, Medical, Military & Aerospace, Security, Test & Measurement, Other

Nethra Am2045 Block Diagram

Nethra's Am2045 massively parallel processor array (MPPA) provides 1 TeraOPS, 50 GMACS and 202 GSADs of fixed-point processing compute for embedded systems in a single chip with over 300 cores. Power consumption is 5 to 10 Watts depending on the application. Inter-processor communication uses a patented, self-synchronizing, switched fabric, which eliminates timing and data synchronization problems. The MIMD fabric is capable of supporting complex software programs that FPGAs or other massively-parallel chips may have difficulty expressing.

The chip has 336 fixed-point, 32-bit RISC processors containing 672 ALUs, in a tiled array of 42 'brics'. Each bric has 4 streaming RISC processors (SR), and 4 streaming RISC processors with DSP extensions (SRD). The cores operate at 300 MHz. Distributed memory includes eight 2-kbytes SRAM blocks per bric, plus dedicated data/instruction memory for each processor. RAM blocks may be clustered for more capacity. SR and SRD cores include 32-bit operations (or dual 16-bit or quad 8-bit SIMD operations).

The cores can execute, loop, receive input, and send output all in one cycle. SRD cores have three ALUs including a barrel-shifter, multiplier, and single-cycle sum of absolute differences (SAD). SRs are compact processors for tasks such as steering data-streams or data preparation, for consistently high SRD throughput. Multiplication is 32x32-bit with 64-bit accumulation, or dual 16-bit with dual 32-bit results. Primary IO for embedded systems includes four 32-bit bi-directional GPIOs that can be partitioned into 16-bit, single-bit, and multi-bit use. GPIO aggregate bandwidth is 13 Gbps from all 128-bits. GPIO supports glue-less connection to HD-SDI SERDES chips, ADCs, DACs, FPGAs, and more.

External memory support includes two (8-port) 32-bit SDRAM interfaces for 3.2 Gbytes/s peak bandwidth. Software configuration loading can be done via PCIe, GPIO, host CPU interface, serial Flash, or JTAG. The package is a thermally enhanced flip-chip BGA at 31x31x3.2 mm, with 896 balls at a 1 mm pitch, and is RoHS compliant. Commercial temperature range is Tj = 0° to 85° C; industrial range is available on request.