Targets: Communication & Wired, Imaging & Video

Tilera Tile64 Block Diagram

The Tile64 processor SoC (system on chip) has 64 full-featured processor cores integrated with four DDR2-memory controllers with ECC (error-correcting code), two 10-Gbps, four-lane PCIe (Peripheral Component Interconnect Express) interfaces, two XAUI (10-Gbit-attachment-unit-interface) 10-GbE (Gigabit Ethernet controllers), two 1-Gbit RGMII (reduced-Gigabit media-independent-interface) Ethernet controllers, and 64-bits of flexible I/O that can support HD video input or other high-speed interfaces. The device includes 5-Mbytes of cache, and each processor core can independently run a full operating system, such as Linux. It is available in speeds of 600 to 900 MHz.

Tilera based the Tile64 family on a tiled multicore architecture with a mesh-based on-chip interconnect. The mesh architecture delivers as much as 32 Tbps of interconnect bandwidth between the cores and allows scaling the architecture beyond hundreds of cores. In addition to multicore processors, Tilera also offers turnkey PCIe appliance boards and a suite of multicore software-development tools.