Western Design Center

Western Design Center


W65C265S

Targets: Automotive, Consumer, Industrial, Medical

The W65C265S is the 16–bit extension of the 65xx microcontroller family. Along with increasing the memory space to 16-Mbyte with a full external memory bus (8–bit data and 24 bit address bus) for flexible system design, the W65C265S includes 3 additional UARTs, increased GPIO, Parallel Interface Bus, and twin tone generators (can perform DTMF signaling). Similar to the W65C134S, the W65C265S has a built–in debug monitor ROM and libraries. A reference design with operating system kernel, display, ToD, data communications and power management software is available.

The hard core IP (intellectual property) is in the industry standard GDSII format. The buffer ring has been designed with off-chip drivers, including latch-up and ESD protection. When the core is embedded, the off-chip buffer ring is replaced with OCB (On-Chip-Bus) interface ring. The abstract cell is the connecting points with labels that provide core verification and system verification. WDC's test programs require that all test pins be compared to the standard test vendors.