[Editor's Note: This was originally posted on the Embedded Master] 

The low power thresholds for processor devices continue to drive downward, but what does it take to drive those energy thresholds ever lower? In many cases, it is possible to reduce a processor’s active current draw by migrating to a more aggressive silicon node, but this comes at the cost of standby power or leakage current. To balance between lower active and standby power, processors rely on low leakage silicon variants and optimally sized transistors within each block of the architecture.

Øyvind Janbu, CTO at Energy Micro, points out that designing circuits that are going to be enabled 100% of the time, such as power supervision circuits with brown-out and power-on-reset functions, is challenging to design to an energy budget of a few nA of current. As with all parts of the processor, chip architects trade-off between speed, energy draw, and accuracy at each resource block to best meet the needs of the specific function and the overall system requirements. He believes that because flash memory is power hungry and slow, in time, it will be replaced by other non-volatile technologies in many cases.

Janbu also feels that some of the challenges when designing for extremely low power chip designs are similar to those faced by RF designers. He believes the accuracy of simulation models of transistors are being pushed outside their intended operating region, and this means that the architects must specify sufficient margins so that the designs still work in volume production. There is a need for more extracted layout simulations because of high impedant nodes due to extremely low currents.

Internal voltage regulators are another low power challenge as microprocessors continue to move into more aggressive silicon nodes. While using internal voltage regulators helps reduce active power consumption, the challenge lies in designing voltage regulators and voltage references that have zero quiescent current, so as to not sacrifice the standby power consumption. The voltage regulator and voltage reference are basically the reason why microprocessors made in 0.18 um or smaller silicon nodes have standby current consumption in the tens of uA range.

The future direction of low power processors may center on modular architectures because driving to extremely low power requirements increasingly requires a rethinking of the fundamental architecture of each module. This rethinking increases the design time and risk of the processor, especially when the architects are exploring and implementing new and unproven approaches. However, as the market finds more uses for low power devices, the increased volumes will provide the needed offsets to incur the longer design cycles and higher risk to push the power threshold even lower.

[Editor's Note: This was originally posted on the Embedded Master] 

In the previous post in this series I pointed out that the “sweet spot” clock rate for active power consumption for some microcontrollers is lower than the maximum operating clock rate for that part. However, looking only at the rated power consumption of these microcontrollers at a steady always-on operating state ignores the fact that many low-power microcontrollers employ on-chip resources that can significantly impact the overall energy consumption of the part as the system transitions through multiple operating scenarios.

For low power applications, designers usually focus on the overall operating system energy draw rather than the peak draw. This focus on overall power efficiency justifies the additional design, build, and testing complexity of using low power and sleep modes when the system does not need to draw on the full processing capacity of the processor. In fact, many low power constrained systems spend the majority of their operating time in some type of sleep mode and transition to full active mode only when needed. This relationship begins to hint at why using only a single uA/MHz benchmark is insufficient to evaluate a processor’s energy performance.

There is a variety of low power modes available to processor architectures. Shutting down just the CPU and leaving all of the other on-chip resources functional is one type of sleep mode. Deeper sleep modes can turn off individual or all peripherals until the only on-chip resource drawing current is for RAM retention. Always-on resources may include a power supervisor circuit with brown-out and power-on-reset functions; these functions must be enabled 100% of the time because the events they are designed to detect cannot be predicted.

So in addition to active power draw, low power designers need to understand the system’s static or leakage current draw when the system is inactive. Another important metric is wake-up-time – the amount of time it takes the system to transition from a low-power mode to the active operating mode because the system clock needs to stabilize. The longer it takes the system clock to stabilize, the more energy is wasted because the system is performing no useful work during that time.

A DMA controller is an on-chip resource that affects a system’s power consumption by offloading the task of moving data from one location to another, say from a peripheral to memory, from the expensive CPU to the much cheaper to operate DMA controller. The following chart from an Atmel whitepaper demonstrates the value of using a DMA controller to offload the CPU, especially as the data rate increases. However, effectively using the DMA can add a level of complexity for the developer because using the DMA controller is not an automated process.

Some microcontrollers, such as from Atmel and Energy Micro, allow developers to configure the DMA controller and peripherals, through some type of peripheral controller, so that they can collect or transmit data autonomously without waking the CPU. On some devices, the autonomous data transfer can even include direct data transfers from one peripheral to another. The following chart from Energy Micro’s technology description demonstrates the type of energy reduction autonomous peripherals can create. The caveat is that the developer needs to create the highly autonomous setup as there are no tools that can perform this task automatically at this time.

On-chip accelerators not only speed up the execution of frequent computations or data transformations, they also do it for less energy than performing those functions with a software engine. Other types of on-chip resources that save energy draw can include ROM-based firmware, such as being adopted by NXP and Texas Instruments on some of their parts. There are countless approaches available to chip architects to minimize energy consumption, but they each involve trade-offs in system speed, current consumption, and accuracy that are appropriate differently to each type of application. This makes it difficult to develop a single benchmark for comparing energy consumption between processors that overlap capabilities but target slightly different application spaces.

[Editor's Note: This was originally posted in the Embedded Master] 

In the previous post in this series I asked whether reporting uA/MHz is an appropriate way to characterize the energy profile of a processor. In this post, I assume uA/Mhz is appropriate for you and offer some suggestions of additional information you might want processor vendors to include with this benchmark when they use it. I will explore how uA/MHz is insufficient for many comparisons in the follow-on post in this series.

One problem with reporting a processor’s power draw as uA/MHz is that this value is not constant across the entire operating range of the processor. Consider the chart for the Texas Instruments MSP430F5438A operating at 3V, from 256-kbyte Flash, and with an integrated LDO. This processor has an operating range up to 25MHz, and the value of uA/MIPS ranges from 230 to 356 uA/MIPS across the full operating range. Additionally, the energy sweet spot for this device is at 8MHz. Using the part at higher (and lower) clock rates consumes more energy per additional unit of processing performance.

Adrian Valenzuela, TI MSP430 MCU Product Marketing Engineer at Texas Instruments shares that many designers using this part operate it at its energy sweet spot of 8MHz precisely because it is most energy efficient at that clock rate rather than at its highest operating speed.

The chart for Microchip’s PIC16LF1823 device illustrates another way to visualize the energy sweet spot for a processor. In this example, the energy sweet spot is at the “knee” in the curve, which is at approximately 16 MHz – again short of the device’s maximum operating clock rate of 32 MHz. 

At a minimum, if a processor vendor is going to specify a uA/MHz (or MIPS) metric, they should also specify the operating frequency of the device to realize that energy efficiency sweet spot. To provide a sense of the processor’s energy efficiency across the full operating range, the processor vendor could include the uA/MHz metric at the device’s highest operating frequency – the implied assumption is that the energy efficiency varies with clock rate in some proportion between these two operating points.

Using a single-value uA/MHz as an energy metric is further complicated when you consider usage profiles that include waking-up from standby or low power modes. In the next post in this series I will explore the challenges of comparing energy efficiency between different processors when the benchmarking parameters differ, such as what kind of software is executing, what is the compiler and memory efficiency, and what peripherals are active?