Targets: Computers & Peripherals, Industrial, Military & Aerospace, Motor Control

The TS68020, TS68882, and TS68C000 are on product end-of life notification with a last time buy date of November 22, 2010.

The TS68040 is a 32-bit virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide high performance in a monolithic HCMOS device. It integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit, and fully independent instruction and data demand-paged memory management units, including 4-kbytes of independent instruction and data caches. Instruction execution parallelism relies on using multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture, including separate physical caches for both instruction and data accesses. The TS68040 directly supports cache coherency in multimaster applications with dedicated on-chip bus snooping logic.

The TS68302 VLSI device is a multichannel communications device that may be configured to support ISDN (integrated services digital network) basic rate and terminal adapter applications. The TS68302 supports concurrent operation of different protocols.

The TS68EN360 QUICC (QUad Integrated Communication Controller) is a one-chip integrated microprocessor and peripheral combination that targets controller applications, especially communications activities. The QUICC can be described as a next-generation TS68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term "quad" comes from the fact that there are four SCCs (serial communications controllers) on the device; however, there are actually seven serial channels: four SCCs, two SMCs (serial management controllers), and one SPI (serial peripheral interface).