Targets: Automotive, Communication & Wired, Consumer, General Purpose, Security

EnSilica eSi-3200 Block Diagram

The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores from EnSilica. It targets low-cost and low-power applications that require more computational power or a larger address space than is provided by the 16-bit eSi-1600 and that are able to be implemented using on-chip memory. The cacheless memory architecture of the eSi-3200 allows for deterministic performance, making it suitable for hard real-time control applications.

The core employs a 5-stage pipeline and static branch prediction. The eSi-3200's instruction set includes arithmetic and logical instructions (including barrel-shift, multiply and divide), comparisons, load and stores, branches and calls as well as system level instructions to control interrupts and enter lower power states. There are optional instructions and addressing modes available, and developers can add their own user-defined instructions and registers. Instructions are encoded in either 16 or 32-bits, depending upon the size of the operands and the type of instruction. All of the commonly used instructions can be encoded in 16-bits.

On 65nm LP technology the processor typically achieves a maximum clock rate of 425MHz. It has a core die area of 0.025mm2 and consumes 0.013mW/MHz including caches when synthesized for a 350MHz clock rate. The basic configuration starts at 15k gates. Hardware debug facilities include hardware breakpoints, watchpoints, null pointer detection and single-stepping for debugging of ROM, FLASH and RAM based programs.