Lattice Semiconductor

Lattice Semiconductor


Targets: Automotive, Communication & Wired, Computers & Peripherals, Consumer, General Purpose, Industrial

Lattice Semiconductor LatticeMico32 Block Diagram

The LatticeMico32 is a configurable 32-bit Harvard architecture soft microprocessor core for Lattice Field Programmable Gate Array (FPGA) devices. By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a Reduced Instruction Set Computer (RISC) architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set. The associated LatticeMico32 System Development Tools enable designers to implement microprocessor designs. The tools enable processor platform definition, software development and debug. The LatticeMico32 is available as source code under the Lattice open IP (intellectual property) core license.

The LatticeMico32 System is used to implement the LatticeMico32 soft microprocessor and attached peripheral components in a Lattice FPGA. It is based on the Eclipse C/C++ Development Tools (CDT) environment. The LatticeMico32 System contains two integrated tools that combine with Lattice's design software (Diamond and ispLEVER) to coordinate the building of an embedded processor system on an FPGA device and write the software to drive it.

The Mico System Builder (MSB) generates platform descriptions and associated HDL for hardware implementation. Within MSB, developers choose peripheral components to attach to the LatticeMico32, as well as specify the connectivity between the peripheral components.

The C/C++ Software Project Environment (SPE) and Debugger is used to develop the code that runs on platforms created with MSB. It interfaces via a command line to compiler, assembler, linker, and debugger tools. The Lattice GNU-based compiler tools provide the appropriate compiler, assembler, linker, and debugger, if desired. It includes a target Instruction Set Simulator (ISS).

The generated LatticeMico32 core and selected peripheral component HDL codes are available through an open IP core licensing agreement, while the GNU-based compiler, assembler, linker, and debugger are licensed under the GNU GPL agreement.