Lattice Semiconductor's open-source LatticeMico32 soft microprocessor core combines a full 32-bit-wide instruction set with 32 general-purpose registers. Designers can customize the microprocessor core to suit a variety of applications. The microprocessor has a Harvard architecture with independent instruction paths and datapaths. These paths terminate in individual Wishbone buses, which Lattice based on the Wishbone specifications defined by OpenCores. The buses provide a standard mechanism for connecting the microprocessor to a variety of peripherals and memory controllers. Peripherals include GPIO (general-purpose-input/output), SPI (serial-peripheral-interconnect), I²C (inter-integrated-circuit), trispeed-Ethernet-MAC (media-access-controller), DDR1, DDR2, and DMA controllers.
The LatticeMico32 license agreement is downloadable from the Lattice Web site. The license preserves the open nature of the core by permitting use alongside proprietary designs and allows hardware implementation and distribution without the need for a subsequent license agreement. This feature provides users with visibility into the microarchitecture's flexible implementation and portability to ASICs or future FPGAs. The Mico System Builder (MSB) tool generates LatticeMico32-based systems in Verilog. The LatticeMico32 System comes with GNU-based C/C++ software-development tools and the GDB (GNU debugger).
Lattice also provides the open-source 8-bit LatticeMico8, the 8051, 68xx series, PIC, and 6502 microcontrollers through its partners Cast, Digital Core Design, and Western Design Center.