Synopsys

Synopsys


DesignWare ARC 605

Targets: Automotive, Communication & Wired, Consumer, General Purpose

The configurable, 5-stage ARC 605 processor is suitable for embedded control and computing functions within system-on-chips (SoCs). The core is designed for hard real-time processing, where high speed and deterministic response are required. Optionally, designers may incorporate custom instruction extensions to achieve application performance levels unattainable with fixed architecture cores. The configurable architecture allows SoC designers to include only the processor features that are required for their specific application.User-defined instruction and register extensions can deliver 5 to 100 times performance improvement for critical routines.

The cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation. The ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit-only instruction sets. The JTAG debug port and optional embedded hardware breakpoints facilitate software debug. The ARC 605 core is delivered as synthesizable RTL source code (Verilog), and it is fully compatible with industry standard design methodologies and tool flows.