Targets: Audio, Consumer, General Purpose, Industrial, Motor Control, Security, Test & Measurement

XMOS XS1-G XCore Block Diagram

The XS1-G is a family of general-purpose Software Defined Silicon devices. It consists of members with 1, 2, and 4 processor cores. Each core supports up to 8 concurrent real-time tasks (400MIPS) with 5ns I/O granularity that enable it to target basic to advanced systems.

Each I/O port has a 5ns precision time stamping capability that is useful in time-sensitive networking applications such as networked audio, low-latency control systems, and automation applications. This time stamping uses local port time, and it can be combined with a higher bit-count core timer to build precision timers of arbitrary size. Incoming packets are time stamped for priority processing and reordering, and outgoing messages can be sent to the I/O with a "send-at" command that the port will use to assert at the specified time to create precise waveforms.

XMOS XS1-G XLink Block Diagram

The precise timing and responsiveness means the XS1-G devices are appropriate for PWM applications such as LED displays, motor control and mechanical interfaces. Precise waveforms are created with a high-level language design flow and take advantage of the guaranteed response times in the ports. A single XCore tile can drive up to 64 PWM channels with 100ns resolution, with 8 to 10ns resolution. An application example is a 1-bit DAC for a class-D amplifier. It takes 4 threads (50% of the resources) of an XCore to generate a stereo audio waveform by driving a 100MHz sigma-delta channel into a discrete component amplifier.

Interprocess communication in XMOS devices is based on tasks (or threads or processes) passing data to each other using a channel-based messaging mechanism called XLink. This abstracts the communications to a named-variable format that is familiar to software designers - the compiler sorts out the hardware details. There is no logical difference for threads communicating in the same processor, in the same chip, or in multiple chips. Distributed intelligence networks fit naturally into this approach. The design tools are all web-based.