Targets: Automotive, Communication & Wired, Consumer

ARM ARM1136J-S/ARM1136JF-S Block Diagram

The ARM1136J-S and ARM1136JF-S processor cores feature the ARM v6 instruction set with media extensions, ARM Jazelle technology for efficient embedded Java execution, ARM Thumb code compression, and optional floating point coprocessor. These features make it suitable for networking, consumer, and automotive infotainment applications such as network switches and routers, digital TV, games consoles, in car entertainment, and navigation equipment.

These processor cores are high performance integer processors with an 8-stage integer pipeline, separate load store and arithmetic pipelines, branch prediction and return stack that can deliver up to 660 Dhrystone 2.1 MIPS in a 0.13-µm process. SIMD media processing extensions offer up to 1.9 times acceleration of media-processing tasks such as MPEG4 encode.

The instruction and data cache sizes are configurable, and designers can add optional TCMs (Tightly Coupled Memories) to accelerate interrupt handling and data processing. The ARMv6 memory system architecture accelerates the operating system context switching.

The processor cores feature AMBA 2.0 AHB interfaces that are compatible with a system IP (intellectual property) and peripherals and speed up instruction and data access. The vectored interrupt interface and low-interrupt-latency mode speeds up interrupt response and real-time performance. The ARM1136JF-S also features an integrated floating-point coprocessor, which makes it suitable for embedded 3D-graphics applications.

The ARM11 core was developed and integrated in parallel with the ARM11 PrimeXsys Platform to ensure a fully compatible, high performance, extendable system. As a result, the ARM11 PrimeXsys Platform provides the optimum route to implement an ARM11 core-based design.