ARM11 MPCore

Targets: Communication & Wired, Imaging & Video

ARM ARM11 MPCore Block Diagram

The ARM11 MPCore synthesizable multicore processor implements the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to an aggregate 2600 Dhrystone MIPS of performance for systems running multiple applications on a single device such as media bridging network devices, network connected set top boxes, for imaging applications. The size of both data and instruction cache can be configured between 16- and 64-kbytes across each processor.

The ARM11 MPCore supports the ARMv6 architecture, with SIMD media extensions for next-generation rich multimedia and convergent devices and ARM Jazelle Java acceleration. It also features configurable L1 caches, 64-bit AMBA AXI interfaces, Vector Floating Point coprocessors, and programmable interrupt control and distribution.

The processor supports Adaptive Shutdown of unused processors to enable dynamic power consumption as low as 0.3749 mW/MHz from a generic 130 nm process excluding cache. ARM IEM (Intelligent Energy Manager) can further reduce consumption to as low as 0.30mW/MHz by dynamically predicting the required performance and lowering the required voltage and frequency. The ARM11 MPCore enables designers to view the core as a single "uniprocessor".

The ARM11 MPCore provides software portability across single core and multi-core designs. It supports a fully coherent data cache, providing the designer with flexibility across symmetric and asymmetric multiprocessing, or any combination of either style of multiprocessor design. The ability to cache shared data increases system performance while enabling workloads to be balanced between processors increases system responsiveness with multitasked applications.

The ARM11 MPCore provides enhanced memory throughput of 1.3 Gbytes/sec from a single CPU, and an implementation that delivers greater performance at lower frequencies than with single processor designs.