Targets: Automotive, Communication & Wired, Computers & Peripherals

ARM ARM968E-S Block Diagram

The ARM968E-S macrocell is a fully synthesizable 32-bit RISC core aimed at embedded real-time applications such as wireless LAN, Firewire, SCSI, mass storage devices, and automotive applications, and it is the smallest, lowest power ARM9E family core to date. The core implements the ARMv5TE instruction set that includes 16-bit fixed point DSP instructions to accelerate signal processing algorithms, as well as supporting the Thumb 16-bit instruction set for high code density. The ARM and Thumb instruction sets can be mixed to support application requirements for speed and code density. The fixed-point DSP instruction extensions reduce the need for separate DSP processors. The code written for the ARM968E-S is forwards compatible with the ARM10E family. The instruction set can be extended for specific requirements using coprocessors. It also features an enhanced 16x32-bit multiplier capable of single cycle MAC operations.

The ARM968E-S core has separate directly connected instruction and data tightly coupled memory (TCM), which have flexible sizes. The dual banked data TCM provides full bandwidth access. Since the core targets hard real time applications that have deterministic memory access, there is no cache. The ARM968E-S also features a dedicated AHB-lite slave Direct Memory Access (DMA) port and dual banked data TCM to enable the core and a DMA controller to share access to TCM.

The low latency AHB-lite bus master interface and the low latency AHB-lite bus slave DMA interface reduce power consumption and improve responsiveness. The ARM968E-S supports ARM's real-time trace technology with the optional ETM9 Embedded Trace Macrocell.