MIPS Technologies

MIPS Technologies


Targets: Audio, Automotive, Communication & Wired, Computers & Peripherals, Consumer, Imaging & Video, Industrial, Mobile & Wireless

MIPS Technologies 1004K Block Diagram

MIPS Technologies' MIPS32 1004K coherent processing system (CPS) is an embedded multi-threaded, multiprocessor licensable IP (intellectual property) core targeting vertical applications including digital home entertainment, home networking and office automation. The 1004K CPS optimizes CPU performance on a shared memory system, enabling multiple functions and applications to run concurrently under symmetric multiprocessing (SMP)-based operating systems. The 1004K CPS is comprised of 1-4 multi-threaded cores, connected via a coherence management unit to maintain coherency between the L1 caches in each CPU. The system includes an optional block to provide coherency on data transfers from I/O peripherals, enabling additional performance by offloading I/O coherency schemes typically run in software as part of the operating system.

The coherent processing system also includes a global interrupt controller that accepts up to 256 interrupts and distributes them down to the cores, or even hardware threads within each core. The whole system can be used with the MIPS L2 cache controller (available separately), which connects to the coherence management unit via an extended 256-bit wide interface for optimized throughput between the coherent system and the L2 cache. An EJTAG and a "coherence-aware" PDtrace (program and data trace) block rounds out the system, providing synchronized visibility into each of the CPU cores and the coherency units in the system via development tools.

The 1004K CPS is available in two versions: the 1004Kc using integer cores, and the 1004Kf with a floating point unit in each core.