Boosting energy efficiency – Energy debugging

Monday, April 4th, 2011 by Oyvind Janbu

Using an ultra low power microcontroller alas does not by itself mean that an embedded system designer will automatically arrive at the lowest possible energy consumption.  To achieve this, the important role of software also needs to be taken into account.  Code needs to be optimized, not just in terms of functionality but also with respect to energy efficiency.  Software has perhaps never really been formally identified as an ‘energy drain’ and it needs to be.  Every clock cycle and line of code consumes energy and this needs to be minimized if best possible energy efficiency is to be achieved.

While the first two parts of this article have proposed the fundamental ways in which microcontroller design needs to evolve in the pursuit of real energy efficiency, so this third part considers how the tools which support them also need to change.  Having tools available that provide developers with detailed monitoring of their embedded systems’ energy consumption is becoming vital for many existing and emerging energy sensitive battery-backed applications.

As a development process proceeds, code size naturally increases and optimizing it for energy efficiency becomes a much harder and time-consuming task.  Without proper tools, identifying a basic code error such as a while loop that should have been replaced with an interrupt service routine can be difficult.  Such a simple code oversight causes a processor to stay active waiting for an event instead of entering an energy saving sleep mode – it therefore matters!  If these ‘energy bugs’ are not identified and corrected during the development phase then they’re virtually impossible to detect in field or burn-in tests.  Add together a good collection of such bugs and they will have an impact on total battery lifetime, perhaps critically so.

In estimating potential battery lifetimes, embedded developers have been able to use spreadsheets provided by microcontroller vendors to get a reasonable estimation of application behavior in terms of current consumption.  Measurements of a hardware setup made by an oscilloscope or multimeter and entered into spreadsheets can be extrapolated to give a pretty close estimation of battery life expectancy.  This approach however does not provide any correlation between current consumption and code and the impact of any bugs – the application’s milliamp rating is OK, but what’s not known is whether it could be any better.

With a logic analyzer a developer gets greater access to the behavior of the application and begins to recognize that ‘something strange’ is going on.  Yes it’s a ‘code view’ tool, and shows data as timing diagrams, protocol decodes, state machine traces, assembly language or its correlation with source level software, however it offers no direct relationship with energy usage.

Combine the logic analyzer, the multimeter, and the spreadsheet and you do start to make a decent connection between energy usage and code, but the time and effort spent in setting up all the test equipment (and possibly repeating it identically on numerous occasions), making the measurements and recording them into spreadsheets can be prohibitive if not practically impossible.

Low power processors such as the ARM Cortex-M3 however are already providing a SWO (serial wire output) that can be used to provide quite sophisticated and flexible debug and monitoring capabilities that tool suppliers can harness to enable embedded developers to directly correlate code execution with energy usage.

Simple development platforms can be created which permanently sample microcontroller power rail current consumption, convert it, and send it along with voltage and timing data via USB to a PC-based energy-to-code profiling tool.  Courtesy of the ARM’s SWO pin, the tool can also retrieve program counter information from the CPU.  The coming together of these two streams of data enables true ‘energy debugging’ to take place.

Provided that current measurements have a fairly high dynamic range, say from 0.1µA to 100mA, then it’s possible to monitor a very wide and practical range of microcontroller current consumption.  Once uploaded with the microcontroller object code, the energy profiling tool then has all the information resources it needs to accurately correlate energy consumption with code.

The energyAware Profiler tool from Energy Micro shows the relationship between current consumption, C/C++ code, and the energy used by a particular function. Clicking on a current peak, top right, reveals the associated code, bottom left.

The tool correlates the program-counter value with machine code, and because it is aware of the functions of the C/C++ source program, it can then readily indicate how energy use changes as various functions run.  So the idea of a tool that can highlight to a developer in real time, an energy-hungry code problem comes to fruition.  The developer watches a trace of power versus time, identifies a surprising peak, clicks on it and is immediately shown the offending code.

Such an ability to identify and rectify energy drains in this way and at an early stage of prototype development will certainly help reduce the overall energy consumption of the end product, and it will not add to the development time either, on the contrary.

We would all be wise to consider the debug process of low power embedded systems development as becoming a 3-stage cycle from now on:  hardware debugging, software functionality debugging, and software energy debugging.

Microcontroller development tools need to evolve to enable designers to identify wasteful ‘energy bugs’ in software during the development cycle.  Discovering energy-inefficient behavior that endanger battery lifetime during a product field trial is after all rather costly and really just a little bit too late!

When is single better than multiple?

Wednesday, March 30th, 2011 by Robert Cravotta

For decades, many embedded designs used separate processors for handling the signal and control processing. Part of the reason for using separate and different types of processors is that the data and processing characteristics of control and signal processing are different enough to warrant different implementations. Control processing is characterized by frequent context switches as the control software must handle different asynchronous events so as to minimize the latency between when an event occurs and when the controller responds to that event. Microcontroller architectures that specialize in control processing usually include circuitry that enables them to detect and respond to interrupts quickly and deterministically.

In contrast, signal processing is characterized by very few context switches. Rather, signal processing exhibits relatively repetitive and predictable processing – however, the amount of computing that must be performed at each data point is usually substantial and overloads traditional microcontroller architectures. Signal processing architectures trade-off efficient context switching for efficient loop processing via special loop instructions and data handling via additional buses.

Because controllers and signal processors differ so much at the architectural level, the skills required to program them are different and the tools to develop with them are different. Managing two different processors simplifies partitioning the processing tasks, but it also increases the complexity of integrating between the two processing systems for the design team.

Within the last decade, a hybrid processing architecture emerged that combined control and signal processing into a single instruction stream. The most recently used label for such processors is digital signal controllers (DSC) which acknowledges its combined architectural trade-offs. DSCs are able to perform context switching like a microcontroller, but they are also able to process light weight signal processing tasks better than a microcontroller. However, they are not capable of handling heavy-lifting signal processing as well as dedicated signal processing architectures.

Hybrid architectures and the development tools to work with them have matured. Hybrid architectures allow a development team to use the same processor architecture throughout each part of the design which supports using the same instruction set and same development tools. However, the interface between the controller and signal processing tasks is limited to the architectural trade-offs that the processor architect made. If the trade-offs that were made match the needs for the project it is being used in, then all is well, but any mismatch will affect the development team’s implementation options.

When is using the single instruction stream benefit of a DSC or hybrid architecture better than using the multiple instruction stream approach of multiple and different types of processors in a design? Have you made this trade-off decision with any of your designs? When did you choose one over the other and why?

Touch with the Microsoft Surface 2.0

Tuesday, March 29th, 2011 by Robert Cravotta

The new Microsoft Surface 2.0 will become available to the public later this year. The technology has undergone significant changes from when the first version was introduced in 2007. The most obvious change is that the dimensions of the newer unitis much thinner, so much so, that the 4 inch thick display can be wall mounted – effectively enabling the display to act like a large-screen 1080p television with touch capability.Not only is the new display thinner, but the list price has nearly halved to $7600. While the current production versions of the Surface are impractical for embedded developers, the sensing technology is quite different from other touch technologies and may represent another approach to user touch interfaces that will compete with other forms of touch technology.

Namely, the touch sensing in the Surface is not really based on sensing touch directly – rather, it is based on using IR (infrared) sensors the visually sense what is happening around the touch surface. This enables the system to sense and be able to interact with nearly any real world object, not just conductive surfaces such as with capacitive touch sensing or physical pressure such as with resistive touch sensing. For example, there are sample applications of the Surface working with a real paint brush (without paint on it). The system is able to identify objects with identification markings, in the form of a pattern of small bumps, to track those objects and infer additional information about them that other touch sensing technologies currently cannot do.

This exploded view of the Microsoft Surface illustrate the various layers that make up the display and sensing housing of the end units. The PixelSense technology is embedded into the LCD layers of the display.

The vision sensing technology is called PixelSense Technology, and it is able to sense the outlines of objects that are near the touch surface and distinguish when they are touching the surface. Note: I would include a link to the PixelSense Technology at Microsoft, but it is not available at this time. The PixelSense Technology embedded in the Samsung SUR40 for Microsoft Surface replaces the five (5) infrared cameras that the earlier version relies on. The SUR40 for Microsoft Surface is the result of a collaborative development effort between Samsung and Microsoft. Combining the Samsung SUR40 with Microsoft’s Surface Software enables the entire display to act as a single aggregate of pixel-based sensors that are tightly integrated with the display circuitry. This shift to an integrated sensor enables the finished casing to be substantially thinner than previous versions of the Surface.

The figure highlights the different layers that make up the display and sensing technology. The layers are analogous to any LCD display except that the PixelSense sensors are embedded in the LCD layer and do not affect the original display quality. The optical sheets include material characteristics to increase the viewing angle and to enhance the IR light transmissivity. PixelSense relies on the IR light generated at the backlight layer to detect reflections from objects above and on the protection layer. The sensors are located below the protection layer.

The Surface software targets an embedded AMD Athlon II X2 Dual-Core Processor operating at 2.9GHz and paired with an AMD Radeon HD 6700M Series GPU using DirectX 11 acting as the vision processor. Applications use an API (application program interface) to access the algorithms contained within the embedded vision processor. In the demonstration that I saw of the Surface, the system fed the IR sensing to a display where I could see my hand and objects above the protection layer. The difference between an object hovering over and touching the protection layer is quite obvious. The sensor and embedded vision software are able to detect and track more than 50 simultaneous touches. Supporting the large number of touches is necessary because the use case for the Surface is to have multiple people issuing gestures to the touch system at the same time.

This technology offers exciting capabilities for end-user applications, but it is currently not appropriate, nor available, for general embedded designs. However, as the technology continues to evolve, the price should continue to drop and the vision algorithms should mature so that they can operate more efficiently with less compute performance required of the vision processors (most likely due to specialized hardware accelerators for vision processing). The ability to be able to recognize and work with real world objects is a compelling capability that the current touch technologies lack and may never acquire. While the Microsoft person I spoke with says the company is not looking at bringing this technology to applications outside the fully integrated Surface package, I believe the technology will become more compelling for embedded applications sooner rather than later. At that point, experience with vision processing (different from image processing) will become a valuable skillset.

Low Power Design: Energy Harvesting

Friday, March 25th, 2011 by Robert Cravotta

In an online course about the Fundamentals of Low Power Design I proposed a spectrum of six categories of applications that identify the different design considerations for low power design for embedded developers. The spectrum of low power applications I propose are:

1) Energy harvesting

2) Disposable or limited use

3) Replaceable energy storage

4) Mobile

5) Tethered with passive cooling

6) Tethered with active cooling

This article focuses on the characteristics that affect energy harvesting applications. I will publish future articles that will focus on the characteristics of the other categories.

Energy harvesting designs represent the extreme low end of low power design spectrum. In an earlier article I identified some common forms of energy harvesting that are publicly available and the magnitude (typically in the μW to mW range) of the energy that are typically available for harvesting.

Energy harvesting designs are ideal for tasks that take place in locations that are difficult to deliver power. Examples include remote sensors, such as might reside in a manufacturing building where the quantity of devices might make performing regular battery replacements infeasible. Also, many of the sensors may be in locations that are difficult or dangerous for an operator to reach. For this reason, energy harvesting systems usually run autonomously, and they spend the majority of their time in a sleep state. Energy harvesting designs often trade-off computation capabilities to fit within a small energy budget because the source of energy is intermittent and/or not guaranteed on a demand basis.

Energy harvesting systems consist of a number of subsystems that work together to provide energy to the electronics of the system. The energy harvester is the subsystem that interfaces with the energy source and converts it into usable and storable electricity. Common types of energy harvesters are able to extract energy from ambient light, vibration, thermal differentials, as well as ambient RF energy.

The rate of energy captured from the environment by the energy harvester may not be sufficient to allow the system to operate; rather, the output of the energy harvester feeds into an energy storage and power management controller that conditions and stores the captured energy in an energy bladder, buffer, capacitor, or battery. Then, when the system is in an awake state, it is drawing energy from the storage module.

The asymmetry between the rate of collecting energy and consuming energy necessitates that the functions the system needs to perform are only executed on a periodic basis that allows enough new energy to be captured and stored between operating cycles. Microcontrollers that support low operating or active power consumption, as well as the capability to quickly switch between the on and off state are key considerations for energy harvesting applications.

A consideration that makes energy harvesting designs different from the other categories in the low power spectrum is that the harvested energy must undergo a transformation to be usable by the electronics. This is in contrast to systems that can recharge their energy storage – these systems receive electricity directly in quantities that support operating the system and recharging the energy storage module.

If the available electricity ever becomes insufficient to operate the energy harvesting module, the module may not be able to capture and transform ambient energy even when there is enough energy in the environment. This key condition for operating means the decision for when and how the system will turn on and off must take extra precautions to avoid drawing too much energy during operation or it will risk starving the system into an unrecoverable condition.

Energy harvesting applications are still an emerging application space. As the cost continues to decrease and the efficiency of the harvesting modules continues to improve, more applications will make sense to pursue in an analogous fashion that microcontrollers have been replacing mechanical controls within systems for the past few decades.

Which is better: faster- or quality-to-market?

Wednesday, March 23rd, 2011 by Robert Cravotta

There are at least two major schools of thought about the best way to release new products – especially products that contain software that can be updated by the user. The faster-to-market approach pushes designs through the development cycle as quickly as possible to release the new product to market before anyone else. A plausible tactic for faster-to-market products that have user-updatable software is to ship the product even while there are still major bugs in the system with the expectation that the development team can create a corrective software patch before the product actually ends up in the hands of the customer. In this scenario, the expectation is that the user will perform a software update before they can even use the product the first time.

The quality-to-market school of thought believes that products should work out of the box without requiring extra effort from the user such as downloading and applying software patches. This philosophy does not preclude the later use of software updates to add or improve features – rather, the out of the box experience is considered an important part of the product’s value.

An argument for the faster-to-market approach is that the user will be able to start benefiting from the product sooner – possibly months sooner because the development team is able to take advantage of the production lead time to bring the product to the desired level of performance. This argument often presumes that the development team would still be working on fixing bugs after shipping a finished product even under the quality-to-market approach. For this approach, the shorter term tactical advantage of using a capability sooner outweighs the probability that some expected features may not work properly.

Likewise, an argument for the quality-to-market approach is that the user will know for certain at the time of purchase what the product will and will not be able to perform. A presumption of this argument is that sometimes a faster-to-market product overpromises what the development team is able to deliver and this leads to customer dissatisfaction because of unmet expectations. For this approach, the longer term strategic advantage of always being able to use the features as-advertised outweighs the probability that a crippled version of the feature will cause you to lose future sales.

There are many companies that side with both of these schools of thought. Which is better? Is one always better or is there a condition when one approach is better than the other? How does your development cycle accommodate one or both of these approaches to releasing a product?

Boosting energy efficiency – Sleeping and waking

Friday, March 18th, 2011 by Oyvind Janbu

While using a 32-bit processor can enable a microcontroller to stay in a deep-sleep mode for longer, there is nevertheless some baseline power consumption which can significantly influence the overall energy budget. However, historically 32-bit processors have admittedly not been available with useful sub-µA standby modes. With the introduction of power efficient 32-bit architectures, the standby options are now complementing the reduced processing and active time.

With the relatively low power consumption many microcontrollers exhibit in deep sleep, the functionality they provide in these modes is often very limited.  Since applications often require features such as real time counters, power-on reset / brown-out detection or UART reception to be enabled at all times, many microcontroller systems are prevented from ever entering deep sleep since such basic features are only available in an active run mode.  Many microcontroller solutions also have limited SRAM and CPU state retention in sub-µA standby modes, if at all.  Other solutions need to turn-off or duty-cycle brown-out and power-on reset detectors in order to save power.

In the pursuit of energy efficiency then microcontrollers need to provide product designers with a choice a sleep modes offering the flexibility to scale basic resources, and thereby the power consumption, in several defined levels or energy modes.  While energy modes constitute a coarse division of basic resources, additional fine-grained tuning of resources within each energy mode should also be able to be implemented by enabling / disabling individual peripheral functions.

There’s little point though in offering a microcontroller with tremendous sleep mode energy consumption if its energy efficiency gains are lost due to the time it takes for the microcontroller to wake up and enter run mode.

When a microcontroller goes from a deep sleep state, where the oscillators are disabled, to an active state, there is always a wake-up period, where the processor must wait for the oscillators to stabilize before starting to execute code.  Since no processing can be done during this period of time, the energy spent while waking up is wasted energy, and so reducing the wake-up time is important to reduce overall energy consumption.

Furthermore, microcontroller applications impose real time demands which often mean that the wake-up time must be kept to a minimum to enable the microcontroller to respond to an event within a set period of time.  Because the latency demanded by many applications is lower than the wake-up time of many existing microcontrollers, the device is often inhibited from going into deep sleep at all – not a very good solution for energy sensitive applications.

A beneficial solution would be to use a very fast RC oscillator that instantly wakes up the CPU and then optionally transfers the clock source to a crystal oscillator if needed. This meets both the real time demands as well as encourages run- and sleep mode duty cycling. Albeit the RC oscillator is not as accurate as a crystal oscillator, the RC oscillator is sufficient as the CPUs clock source during crystal start-up.

We know that getting back to sleep mode is key to saving energy. Therefore the CPU should preferably use a high clock frequency to solve its tasks more quickly and efficiently.  Even if the higher frequency at first appears to require more power, the advantage is a system that is able to return to low power modes in a fraction of the time.

Peripherals however might not need to run at the CPU’s clock frequency.  One solution to this conundrum is to pre-scale the clock to the core and peripherals, thereby ensuring the dynamic power consumption of the different parts is kept to a minimum.  If the peripherals can further operate without the supervision of the CPU, we realize that a flexible clocking system is a vital requirement for energy efficient microcontrollers.

The obvious way for microcontrollers to use less energy is to allow the CPU to stay asleep while the peripherals are active, and so the development of peripherals that can operate with minimum or no intervention from the CPU is another worthy consideration for microcontroller designers.  When peripherals look after themselves, the CPU can either solve other high level tasks or simply fall asleep, saving energy either way.

With advanced sequence programming, routines for operating peripherals previously controlled by the CPU can be handled by the peripherals themselves.  The use of a DMA controller provides a pragmatic approach to autonomous peripheral operation.  Helping to offload CPU workload to peripherals, a flexible DMA controller can effectively handle data transfers between memory and communication or data processing interfaces.

Of course there’s little point in using autonomous peripherals to relieve the burden of the CPU if they’re energy hungry.  Microcontroller makers also need to closely consider the energy consumption of peripherals such as serial communication interfaces, data encryption/decryption engines, display drivers and radio communication peripherals.  All peripherals must be efficiently implemented and optimized for energy consumption in order to fulfill the application’s need for a low system level energy consumption.

Taking the autonomy ideal a step further, the introduction of additional programmable interconnect structures into a microcontroller enable peripherals to talk to peripherals without the intervention of the CPU, thereby reducing energy consumption even further.  A typical example of a peripheral talking to another peripheral would be an ADC conversion periodically triggered by a timer. A flexible peripheral interconnect allows direct hardware interaction between such peripherals, solving the task while the CPU is in its deepest sleep state.

The third part of this three part article explores the tools and techniques available for energy debugging.

Do you have enough budget for your embedded project?

Wednesday, March 16th, 2011 by Robert Cravotta

The word on the street is that budgets for development projects have been shrinking for years – perhaps even decades. If this sentiment is true, how do so many embedded designs make it to production status each year? Is the design quality for these projects more compromised each year? If the projects are over budget each year, how do the companies that fund these projects realize a high enough return on investment to keep justifying starting new designs? I question the validity of the claim that budgets have been shrinking year-in and year-out for ever increasingly complex designs without some offset occurring somewhere.

Perhaps a development team has a smaller budget for developers, but is it done without an increase for the development tools? I have been watching the development tool industry for years to see where the big productivity gains are coming from. Most of what I have observed is incremental improvements in what tools can offload from developers. Also, I do believe companies have been slashing their training budgets, but somehow the projects still get done (maybe not optimally but well enough to justify doing the project in the first place).

Another way that projects might get by with smaller development budgets is through heavy reuse of earlier designs and/or licensed IP (intellectual property). A trend that I have seen increasing over the years is that semiconductor companies are providing more software with their silicon products so that development teams can concentrate their efforts on the value add features rather than the basic functions. In this case, the overall budget is not shrinking so much as it is being transferred to different development teams.

I do not expect that development teams have generous budgets. I do expect that the budgets routinely require creative thinking from the team members as to how to squeeze 10 to 20% more out of the budget to meet the project requirements – but that is the process by which continuous improvement occurs – I doubt it would occur any other way. Are your budgets sufficient or are they too tight to complete your projects? What would you change about your budgeting process if you had your way? Is it possible for budgets to shrink every year and still be able to produce ever more complex designs?

How do you handle obsolescence?

Wednesday, March 9th, 2011 by Robert Cravotta

Producers and users are both involved when a product, component, or technology is slated for obsolescence, but both parties do not always agree that the obsolescence is appropriate. Take for example Microsoft’s efforts to kill Internet Explorer 6 (IE6). The company recently launched a website called ie6countdown.com with the intent to track and encourage people to migrate away from the ten year old web browser. As of February 2011, 12% of worldwide users are still using IE6 as their browser – this represents a sizable group of people that present a support challenge for Microsoft and web content developers. According to Roger Capriotti at Microsoft, their goal is to get the worldwide share down to below 1% because they believe that 1% will allow more sites and IT pros worldwide to make IE6 a low-priority browser.

One thing I was not able to discover on the tracking website is the type of machine these IE6 users are running the browser on. I suspect that the underlying hardware may play a larger role in the continued use of the browser that will be three generations behind the latest browser (IE9) as of March 14th.

For embedded developers, the obsolescence of components can wreak havoc. While the end user may not even be aware of the embedded systems in their end devices, changing the implementation of an embedded system is no trivial task. That is why on many aerospace programs I worked on we specified that the microprocessor that we selected must be available to support a twenty or thirty year support window. Now that did not mean the processor supplier had to keep manufacturing those processors for all of those years, but it did mean that there was a plan to pre-produce and store those processors against some usage plan for that period of time.

Part of the reason for continuing to use the older processors was that it was too risky and expensive to upgrade the system to the latest generation processors. Even though a processor may be fully backwards compatible, the interfaces and timing differences of system events could shift just enough to cause intermittent failures in the end system. To upgrade a processor would entail a complete recertification, and for some systems, that is an unjustifiable expense to only maintain the functionality of a system.

Maintaining older generations of components beyond their production life cycle can also apply to software modules. Changing the operating system in an embedded system may also require a recertification, so it is safer and more cost effective to freeze the operating system at a specific configuration and version.

How do you handle obsolescence – both as a producer and as a user? As a producer, this question is most interesting when your user base wishes to continue using your product beyond your planned production cycle. As a user, this question is interesting as a way to explore different strategies to maintain a frozen design or migrate the design without incurring product killing costs.

Low Power Design Course

Tuesday, March 8th, 2011 by Robert Cravotta

In last week’s Question of the Week I asked “what makes an embedded design low power?” I asked if there was a way to describe low power design such that it accommodates moving the threshold definitions as technology continues to improve. The reader responses encompassed a common theme – that the magnitude of the system’s power consumption is not what defines it as a low power design. Rather, you must take into account the end-use requirements and compare the final implementation with other implementations for analogous functions to confirm that the “low power” implementation completes the function at less cost and/or less energy.

The impetus for this question comes from a new information center about the basics of design that we have added to Embedded Insights to supplement an online course that I recently put together and presented. The course is hosted at EE Times as part of their Fundamentals feature, and it is called Fundamentals of Low Power Design using the Intel Atom Processor.

A challenge in creating the course was to create an approach that imparted useful information to every type of embedded developer – not just the people that were interested in the target processor (the Intel Atom in this case). I developed a spectrum of low power design that expands the sweet spot concept that I have proposed for processor architectures. In this case, the spectrum identifies six (6) different target implementations that share a common goal and available techniques for low power/energy designs – but they may define their thresholds and optimization approaches differently. The categories identified in the spectrum are energy harvesting, disposable, replaceable, mobile, tethered with passive cooling, and tethered with active cooling. I briefly describe each of these categories in the course, and I will follow-up with articles that focus on each one.

The Basics Information Center aggregates and organizes information on the basics for design topics. The inaugural page includes a set of low power optimization datasheets for a number of processor architectures that I researched when developing the course – however, including them in the final version of the course material would disrupt the flow of the sponsored material, so we are providing them as supplemental material. The concepts in the datasheets are a work-in-progress, so we welcome any comments that help us to tweak and fill-in the content so that the lower power spectrum and datasheets become a more useful tool for describing embedded processors. The end goal is to take what we learn from this effort and incorporate it into a parts search engine for the Embedded Processing Directory.

The datasheets currently reflect the organization of the course material; we will probably need to change them to make the information more generally accessible. Please share any ideas or specific information that we can use to refine the datasheets.

Green with envy: Why power debugging is changing the way we develop code

Friday, March 4th, 2011 by Shawn Prestridge

As time passes, consumers demand more from their mobile devices in terms of content and functionality, and this demand has eroded the ability of battery technology to keep up with our insatiable appetite for capability.  The notion of software power debugging is assisting the development engineer to create more ecologically sound devices based on the ability to see how much power is consumed by the device and correlating this to the source code.  By doing statistical profiling of the code with respect to power, an engineer has the ability to understand the impact of their design decisions on the mobile devices that they create.  Armed with this information, the engineer will be able to make more informed decisions about how the code is structured to both maximize battery life and minimize the impact on our planet’s natural resources.

Anyone who has a modern smartphone can attest to their love/hate relationship to it – they love the productivity boost it can provide, the use of GPS functionality to help us find our destination and the ability to be connected to all aspects of their lives, be it via text messaging, e-mail or social networking. But all of this functionality comes at a great cost – it is highly susceptible to the capacity of the battery and can even have a deleterious impact on the life of the battery as the battery can only withstand a certain number of charge cycles.  There are two ways that this problem can be approached: either increase the energy density of the battery so that it can hold a greater mAh rating for the same size and weight or to pay special attention to eliminating extraneous power usage wherever possible.  The problem with the former is that advances in energy storage technology have been far outstripped by the power requirements of the devices they serve.  Thus, we are left with the choice of minimizing the amount of power consumed by the device.

Efforts to reduce the power footprint of a device have been mostly ad-hoc or out of the control of the device’s development engineers, e.g. improvements in wafer technology give the ability to space transistors closer together to cut down on power consumption via reduced capacitances.  However, power debugging gives a modern development engineer the ability to see how their code decisions impact the overall power consumption of the system by tying the measurements of power being supplied to the system with the program counter of the microcontroller.  Power debugging can give you the ability to see potential problems before you go to manufacturing of production hardware.  For example, you may have a peripheral that the engineer thought was deactivated in their code, but in reality is still active and consuming power.  By looking at the power graph, the engineer has the contextual clue that the power consumption of the device is more than it should be and warrants an inspection of the devices that are active in the system that are consuming energy.

Another example of how power debugging can assist an engineer is by looking at the duty cycles of their microcontroller.  A common design paradigm in battery-powered electronics is to wake up from some sort of power-saving sleep mode, do the processing required and then return to the hibernation state.  This is relatively simple to code, but the engineer may not be aware that there is an external stimulus causing the microcontroller to rouse from the sleep mode prematurely and thus causing the power consumption to be higher than it should.  It is also possible that an external signal is occurring more often than was planned in the original design specification.  While this case can be traced with a very judicious use of breakpoints, the problem may persist for quite some time before the behavior is noticed.  A timeline view of the power consumption can foreshorten this latent defect because it can evince these spikes in current and allow the engineer to double-click the spike to see where in the code the microcontroller was executing when the spike occurred, thus providing the engineer with the information necessary to divine what is happening to cause the power requirements to be so high.

Power debugging can also provide statistical information about the power profile of a particular combination of application and board.  This can be used in baselining the power consumption in such a way that if the engineer adds or changes a section of code in the application and then sees the power differ drastically from the baseline, then the engineer knows that something in the code section they just added or modified caused the spike and can investigate further what is happening and how to mitigate it.  Moreover, an engineer can change microcontroller devices to see if the power consumption of one device is lower or higher than that of another device, thus giving a commensurate comparison between the two devices.  This allows the engineer to make very scrupulous decisions about how their system is constructed with respect to power consumption.

It is evident that our consumer society will begin to rely increasingly on mobile devices which will precipitate demand for more capability and – correspondingly – more power from the batteries which drive these devices.  It behooves an engineer to make their design last as long as possible on a single battery charge, so particular attention must be paid to how the design is constructed – both in hardware and software – to maximize the efficiency of the device.  Power debugging gives the engineer the tools necessary to achieve that goal of making a more ecologically-friendly device that makes every electron count.