Targets: Communication & Wired, Computers & Peripherals, Consumer, Digital Power, General Purpose, Industrial, Medical, Mobile & Wireless, Test & Measurement, Other

NXP LPC1300 Block Diagram

The LPC1300 series is part of NXP's LPC1000 family. Based on the Cortex-M3 Rev2 core and designed for embedded 16 and 32-bit applications, the LPC1300 series operates at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC13xx devices includes up to 32-kbytes of flash memory, up to 8-kbytes of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus I²C-bus interface, one UART, four general-purpose timers, and up to 42 general-purpose I/O pins. The LPC1300 also enables in-system programming and in-application programming via on-chip bootloader software. USB Mass Storage and HID class drivers are included on-chip enabling quick setup of USB communication. These drivers are incorporated in ROM, leaving 100% of the user Flash space for the application.