Targets: Audio, Communication & Wired, Computers & Peripherals, Consumer, Digital Power, General Purpose, Imaging & Video, Industrial, Medical, Mobile & Wireless, Motor Control, Security, Test & Measurement, Other

NXP LPC2200 Block Diagram

The NXP LPC2200 series is part of NXP's LPC2000 microcontroller family. These ARM7-based microcontrollers use a 128-bit-wide memory interface and an accelerator architecture to enable 32-bit code execution from Flash at a maximum clock rate of 75 MHz. These microcontrollers integrae up to four interconnected CAN interfaces with advanced acceptance filters and an optional extended temperature range of -40 to +125 °C (LPC2294 only) to target automotive and industrial applications that use the CAN bus. Other integrated features include enhanced timing functions and power monitoring to target medical, communication, and general-purpose applications. For code-size critical applications, the microcontrollers use an alternative 16-bit Thumb Mode that reduces code by more than 30% with minimal performance penalty.

Most LPC22xx microcontrollers are equipped with up to 256-kbyte of on-chip Flash and use in-system (ISP) and in-application (IAP) software to minimize programming time. Each 512-byte line takes 1 ms to program and a single-selector or full erase takes 400 ms. For real-time debug, it uses a Vectored Interrupt Controller (VIC), along with embedded ICE-RT and ETM (Embedded Trace Macrocell). Each microcontroller has a configurable external memory interface with up to four banks (each up to 16 Mb and 8/16/32-bit data width), and an 8-channel, 10-bit A/D converter that offers conversion times as low as 2.44 us.

Several on-chip features combine to reduce chip count, save board space, and lower overall cost. Included are two 32-bit timers (with four capture and four compare channels each), a PWM unit (with six channels), a real-time clock, and a Watchdog timer. Multiple serial interfaces, including two UARTs (16C550), two Fast I²C-bus (400 kbps), and two SPI (one with buffering and variable data-length capabilities), increase design flexibility. A CPU clock, operating at a maximum of 60 to 75 MHz, is available from the on-chip phase-locked loop (PLL). There are up to 112 I/O, each tolerant to 5 V, and there are up to nine edge- or level-sensitive interrupt pins.