Targets: Audio, Automotive, Communication & Wired, Computers & Peripherals, Consumer, General Purpose, Industrial, Mobile & Wireless, Security, Test & Measurement, Other

NXP LPC3100 Block Diagram

The NXP LPC3100 series is part of NXP's LPC3000 microcontroller family. These devices combine an up to 270-MHz ARM926EJ CPU core, High Speed USB 2.0 OTG, up to 192-kbyte SRAM, NAND Flash Controller with available 128-bit AES Decryption Engine (LPC3154/LPC3143), flexible external bus interface, three channel 10-bit A/D and several serial and parallel interfaces.

To optimize system power consumption, the LPC31xx devices have multiple power domains and a flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. The integrated Power Supply Unit (PSU) allows the system to run directly from the battery or the USB power. The available built-in charger allows a Li-Ion battery to be charged from the power supplied by a USB connection or by an AC adapter. The charger also monitors battery voltage, charge current, battery and chip temperature.

The available Stereo Audio CODEC with Class AB Headphone Amplifier is suitable for high-quality audio applications. The available secure One-Time-Programmable (OTP) memory provides a unique ID, the ability to store secure keys/USB product ID, and the option to access JTAG securely.