Targets: Audio, Automotive, Communication & Wired, Computers & Peripherals, Consumer, General Purpose, Imaging & Video, Industrial, Medical, Mobile & Wireless, Motor Control, Test & Measurement, Other

NXP LPC3200 Block Diagram

The NXP LPC3200 series is part of NXP's LPC3000 microcontroller family. Built around a 90-nm, 266-MHz ARM926EJ-S CPU core and a Vector Floating Point (VFP) coprocessor, the NXP LPC32x0 devices target applications that require high performance, high integration, and low power consumption.

The VFP coprocessor increases the speed of calculations by a factor of four to five in scalar mode, and more in optimized vector mode. Advanced process technology optimizes each microcontroller's intrinsic power, and software-controlled features provide best-in-class power management. Each LPC32x0 microcontroller has up to 256-kbyte of internal SRAM, and an external memory controller that supports DDR and SDR SDRAM, SRAM, Flash, and static devices. The external-memory controller can boot-up from NAND Flash, SPI memory, UART, or SRAM. On the LPC3230 and the LPC3250, there is an LCD controller that supports STN and TFT panels, and offers a dedicated DMA controller and programmable display resolution up to 1024 x 768 and up to 16 M colors.

The LPC3240 and LPC3250 microcontrollers have a 10/100 Ethernet MAC with a dedicated DMA controller. Every LPC32x0 microcontroller has a USB interface that supports device, host, and On-The-Go (OTG) operation. There are four standard 16C550 UARTs (one supports IrDA), three high-speed (up to 921,600 bps) UARTs, two Fast I²C-bus (400 Kbps) interfaces with slave, single, and multi-master support, two SPI/SSP ports, and a function for automatic keyboard scanning that supports 8 x 8 keys. There are also two I²S interfaces, each with separate input and output channels. Each channel can be operated independently on three pins, or, with four pins, the input and output of one I²S interface can be used.

Each LPC32x0 microcontroller has a 10-bit, 400-kHz A/D converter with three channels and a touch screen interface, five 32-bit timers with capture/compare channels, a 32-bit timer driven by the real-time clock, eleven PWM channels, and a Watchdog timer. There is a real-time clock with a separate clock and power domain, a dedicated 32-kHz oscillator, a Secure Digital (SD) interface, and an integrated interrupt controller that supports up to 73 interrupt sources. Data movement is managed by an eight-channel, general purpose DMA controller that can be used with SD ports, UARTs, I²S ports, SPI interfaces, or memory-to-memory transfers.

A seven-layer, 32-bit, 104-MHz AHB matrix provides a separate bus for each of the seven AHB masters (D-cache, I-cache, two DMA, Ethernet MAC, USB controller, and LCD controller). This eliminates arbitration delays, except when two masters attempt to access the same slave at the same time.

An on-chip PLL lets the CPU operate up to its maximum rate without a high-frequency crystal. A second PLL enables operation from the 32-kHz real-time clock instead of the external crystal. The core voltage supports 1.35 V for 266 MHz or 1.2 V for 208 MHz, while the I/O ports support 1.8, 2.8, and 3.0 V. The operating temperature range -40 to +85 °C. In ultra-low power mode, the core operates down to 0.9 V. For debugging, LPC32x0 microcontrollers use a JTAG interface with a 2K x 24-bit emulation trace buffer and supports real-time emulation.